<TABLE>
<TR  bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR >
<TD >decode_unit_inst</TD>
<TD >19</TD>
<TD >0</TD>
<TD >3</TD>
<TD >0</TD>
<TD >17</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >get_instruct_inst|ram_disk_inst|altsyncram_component|auto_generated</TD>
<TD >28</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >get_instruct_inst|ram_disk_inst</TD>
<TD >28</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >16</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >get_instruct_inst</TD>
<TD >19</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >17</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|instruct_unit_inst|sub_inst</TD>
<TD >20</TD>
<TD >0</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|instruct_unit_inst|add_inst</TD>
<TD >20</TD>
<TD >0</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|instruct_unit_inst|str_inst</TD>
<TD >20</TD>
<TD >0</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|instruct_unit_inst|sdal_inst</TD>
<TD >20</TD>
<TD >0</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|instruct_unit_inst</TD>
<TD >20</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|right_shift_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|left_shift_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|xor_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|not_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >32</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|or_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|and_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|mod_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|div_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|multi_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|sub_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst|add_cell_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >15</TD>
<TD >0</TD>
<TD >15</TD>
</TR>
<TR >
<TD >ctrl_center_inst|ALU_inst</TD>
<TD >50</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_ram_inst|ram_256x16_inst|altsyncram_component|auto_generated</TD>
<TD >28</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_ram_inst|ram_256x16_inst</TD>
<TD >28</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >16</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_ram_inst</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >14</TD>
<TD >0</TD>
<TD >14</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst|reg_07</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >26</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst|reg_06</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >26</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst|reg_05</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >26</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst|reg_04</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >26</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst|reg_03</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >26</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst|reg_02</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >26</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst|reg_01</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >26</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst|reg_00</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >26</TD>
<TD >0</TD>
<TD >26</TD>
</TR>
<TR >
<TD >ctrl_center_inst|rw_reg_inst</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >49</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >ctrl_center_inst</TD>
<TD >20</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >17</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >sys_init_inst</TD>
<TD >2</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
</TABLE>
